Nios II

E724162

Nios II is a soft-core 32-bit RISC processor architecture developed by Altera (now Intel) for implementation on FPGA devices.

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Statements (50)

Predicate Object
instanceOf 32-bit RISC processor
embedded processor core
soft-core processor architecture
architectureType RISC
bitWidth 32-bit
category FPGA IP core
soft microprocessor core
designedFor customizable embedded systems on FPGAs
developer Altera NERFINISHED
Intel NERFINISHED
documentationPublisher Intel PSG (Programmable Solutions Group) NERFINISHED
ecosystem HAL (Hardware Abstraction Layer) libraries
RTOS support from multiple vendors
feature configurable pipeline depth and performance levels
high-performance configuration for larger FPGAs
small footprint configuration for low-cost FPGAs
hasVariant Nios II/e (economy) configuration NERFINISHED
Nios II/f (fast) configuration
Nios II/s (standard) configuration
implementationType soft-core
intendedPlatform FPGA
introducedBy Altera NERFINISHED
market communications equipment
embedded systems
industrial control
ownedBy Intel NERFINISHED
predecessor Nios NERFINISHED
programmingLanguageSupport C NERFINISHED
C++ NERFINISHED
supports Harvard architecture style instruction and data paths
MMU-less configurations
configurable cache sizes
configurable memory interfaces
custom instructions
debug via JTAG
exceptions
hardware acceleration via custom logic
interrupts
off-chip memory interfaces
on-chip debug modules
on-chip memory
optional memory management features
toolchain GCC-based compiler support
Intel Quartus Prime integration
Platform Designer (Qsys) integration
typicalUseCase embedded control in FPGA-based systems
signal processing on FPGA
system-on-a-programmable-chip designs
usedWith Altera FPGA devices NERFINISHED
Intel FPGA devices NERFINISHED

Referenced by (2)

Full triples — surface form annotated when it differs from this entity's canonical label.

GNU As supportsTarget Nios II