TriCore
E724160
TriCore is a 32-bit microcontroller CPU architecture developed by Infineon that combines RISC, DSP, and microcontroller features for real-time embedded applications.
All labels observed (1)
| Label | Occurrences |
|---|---|
| TriCore canonical | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T8285568 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
Target entity: TriCore Context triple: [QEMU, supportsGuestArchitecture, TriCore]
-
A.
Motorola 68000 family
The Motorola 68000 family is a line of 16/32-bit CISC microprocessors widely used in early personal computers, workstations, and game consoles during the 1980s and early 1990s.
-
B.
Hitachi SH-4
The Hitachi SH-4 is a 32-bit RISC microprocessor known for its use in late-1990s gaming consoles and embedded systems, featuring strong floating-point performance for 3D graphics.
-
C.
Motorola 68851
The Motorola 68851 is an external paged memory management unit (MMU) designed to work with Motorola 68020 processors, providing advanced virtual memory and protection features.
-
D.
Motorola 88000 family
The Motorola 88000 family is a RISC-based microprocessor line developed by Motorola as a high-performance follow-up to its earlier 68000 series, aimed primarily at workstations and embedded systems.
-
E.
Motorola 68020 microprocessor
The Motorola 68020 microprocessor is a 32-bit CISC CPU introduced in the early 1980s that powered many workstations, servers, and Apple Macintosh computers, offering enhanced performance and features over its 68000-series predecessors.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Target entity: TriCore Target entity description: TriCore is a 32-bit microcontroller CPU architecture developed by Infineon that combines RISC, DSP, and microcontroller features for real-time embedded applications.
-
A.
Motorola 68000 family
The Motorola 68000 family is a line of 16/32-bit CISC microprocessors widely used in early personal computers, workstations, and game consoles during the 1980s and early 1990s.
-
B.
Hitachi SH-4
The Hitachi SH-4 is a 32-bit RISC microprocessor known for its use in late-1990s gaming consoles and embedded systems, featuring strong floating-point performance for 3D graphics.
-
C.
Motorola 68851
The Motorola 68851 is an external paged memory management unit (MMU) designed to work with Motorola 68020 processors, providing advanced virtual memory and protection features.
-
D.
Motorola 88000 family
The Motorola 88000 family is a RISC-based microprocessor line developed by Motorola as a high-performance follow-up to its earlier 68000 series, aimed primarily at workstations and embedded systems.
-
E.
Motorola 68020 microprocessor
The Motorola 68020 microprocessor is a 32-bit CISC CPU introduced in the early 1980s that powered many workstations, servers, and Apple Macintosh computers, offering enhanced performance and features over its 68000-series predecessors.
- F. None of above. chosen
Statements (52)
| Predicate | Object |
|---|---|
| instanceOf |
32-bit processor architecture
ⓘ
microcontroller CPU architecture ⓘ |
| architectureWidth | 32-bit ⓘ |
| designedFor | real-time embedded applications ⓘ |
| developer | Infineon Technologies NERFINISHED ⓘ |
| hasApplicationDomain |
automotive electronics
ⓘ
industrial control ⓘ powertrain control ⓘ safety-critical systems ⓘ |
| hasFeature |
DSP
ⓘ
RISC NERFINISHED ⓘ microcontroller features ⓘ |
| hasGeneration |
TriCore 1
ⓘ
TriCore 1.3 NERFINISHED ⓘ TriCore 1.6 NERFINISHED ⓘ TriCore 1.6.1 NERFINISHED ⓘ TriCore 1.6.2 NERFINISHED ⓘ TriCore 1.8 NERFINISHED ⓘ TriCore 1.8.1 NERFINISHED ⓘ TriCore 1.8.10 NERFINISHED ⓘ TriCore 1.8.11 NERFINISHED ⓘ TriCore 1.8.12 NERFINISHED ⓘ TriCore 1.8.13 NERFINISHED ⓘ TriCore 1.8.14 NERFINISHED ⓘ TriCore 1.8.15 NERFINISHED ⓘ TriCore 1.8.16 NERFINISHED ⓘ TriCore 1.8.17 NERFINISHED ⓘ TriCore 1.8.18 NERFINISHED ⓘ TriCore 1.8.19 NERFINISHED ⓘ TriCore 1.8.2 NERFINISHED ⓘ TriCore 1.8.20 NERFINISHED ⓘ TriCore 1.8.21 ⓘ TriCore 1.8.22 NERFINISHED ⓘ TriCore 1.8.23 NERFINISHED ⓘ TriCore 1.8.24 NERFINISHED ⓘ TriCore 1.8.25 NERFINISHED ⓘ TriCore 1.8.5 NERFINISHED ⓘ TriCore 1.8.6 NERFINISHED ⓘ TriCore 1.8.7 NERFINISHED ⓘ TriCore 1.8.8 NERFINISHED ⓘ TriCore 1.8.9 NERFINISHED ⓘ |
| hasProperty |
Harvard architecture elements
ⓘ
integrated interrupt controller ⓘ integrated memory protection unit ⓘ on-chip debug support ⓘ pipelined architecture ⓘ support for real-time operating systems ⓘ |
| supports |
hardware multiply-accumulate operations
ⓘ
single-cycle DSP operations ⓘ |
| usedIn |
Infineon AURIX microcontrollers
NERFINISHED
ⓘ
Infineon TC2xx microcontroller family NERFINISHED ⓘ Infineon TC3xx microcontroller family NERFINISHED ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Subject: TriCore Description of subject: TriCore is a 32-bit microcontroller CPU architecture developed by Infineon that combines RISC, DSP, and microcontroller features for real-time embedded applications.
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.