TriCore
E724160
TriCore is a 32-bit microcontroller CPU architecture developed by Infineon that combines RISC, DSP, and microcontroller features for real-time embedded applications.
Statements (52)
| Predicate | Object |
|---|---|
| instanceOf |
32-bit processor architecture
ⓘ
microcontroller CPU architecture ⓘ |
| architectureWidth | 32-bit ⓘ |
| designedFor | real-time embedded applications ⓘ |
| developer | Infineon Technologies NERFINISHED ⓘ |
| hasApplicationDomain |
automotive electronics
ⓘ
industrial control ⓘ powertrain control ⓘ safety-critical systems ⓘ |
| hasFeature |
DSP
ⓘ
RISC NERFINISHED ⓘ microcontroller features ⓘ |
| hasGeneration |
TriCore 1
ⓘ
TriCore 1.3 NERFINISHED ⓘ TriCore 1.6 NERFINISHED ⓘ TriCore 1.6.1 NERFINISHED ⓘ TriCore 1.6.2 NERFINISHED ⓘ TriCore 1.8 NERFINISHED ⓘ TriCore 1.8.1 NERFINISHED ⓘ TriCore 1.8.10 NERFINISHED ⓘ TriCore 1.8.11 NERFINISHED ⓘ TriCore 1.8.12 NERFINISHED ⓘ TriCore 1.8.13 NERFINISHED ⓘ TriCore 1.8.14 NERFINISHED ⓘ TriCore 1.8.15 NERFINISHED ⓘ TriCore 1.8.16 NERFINISHED ⓘ TriCore 1.8.17 NERFINISHED ⓘ TriCore 1.8.18 NERFINISHED ⓘ TriCore 1.8.19 NERFINISHED ⓘ TriCore 1.8.2 NERFINISHED ⓘ TriCore 1.8.20 NERFINISHED ⓘ TriCore 1.8.21 ⓘ TriCore 1.8.22 NERFINISHED ⓘ TriCore 1.8.23 NERFINISHED ⓘ TriCore 1.8.24 NERFINISHED ⓘ TriCore 1.8.25 NERFINISHED ⓘ TriCore 1.8.5 NERFINISHED ⓘ TriCore 1.8.6 NERFINISHED ⓘ TriCore 1.8.7 NERFINISHED ⓘ TriCore 1.8.8 NERFINISHED ⓘ TriCore 1.8.9 NERFINISHED ⓘ |
| hasProperty |
Harvard architecture elements
ⓘ
integrated interrupt controller ⓘ integrated memory protection unit ⓘ on-chip debug support ⓘ pipelined architecture ⓘ support for real-time operating systems ⓘ |
| supports |
hardware multiply-accumulate operations
ⓘ
single-cycle DSP operations ⓘ |
| usedIn |
Infineon AURIX microcontrollers
NERFINISHED
ⓘ
Infineon TC2xx microcontroller family NERFINISHED ⓘ Infineon TC3xx microcontroller family NERFINISHED ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.