Pro Edition
E660948
Pro Edition is the advanced, high-performance version of Intel's Quartus FPGA design software tailored for large, complex, and high-end device families.
Statements (49)
| Predicate | Object |
|---|---|
| instanceOf |
FPGA design software
ⓘ
software edition ⓘ |
| category |
FPGA development tool
ⓘ
electronic design automation software ⓘ |
| comparedTo | Standard Edition NERFINISHED ⓘ |
| designedFor |
complex FPGA designs
ⓘ
high-end FPGA device families ⓘ large FPGA designs ⓘ |
| developedBy | Intel NERFINISHED ⓘ |
| editionOf | Quartus FPGA design software NERFINISHED ⓘ |
| fullName | Intel Quartus Prime Pro Edition NERFINISHED ⓘ |
| hasAdvantageOver | Standard Edition in capacity and performance NERFINISHED ⓘ |
| hasFeature |
IP catalog integration
ⓘ
Tcl-based automation ⓘ advanced resource utilization reporting ⓘ chip planner ⓘ cross-probing between tools ⓘ design assistant ⓘ floorplanning tools ⓘ project-wide incremental compilation ⓘ scripting interface ⓘ |
| licenseType | commercial software license ⓘ |
| optimizedFor |
Intel 20 nm and smaller process nodes
ⓘ
high-capacity FPGAs ⓘ |
| partOf | Intel Quartus Prime NERFINISHED ⓘ |
| platform |
Linux
ⓘ
Windows ⓘ |
| predecessor | Altera Quartus II NERFINISHED ⓘ |
| supports |
Intel Agilex FPGAs
NERFINISHED
ⓘ
Intel Arria 10 FPGAs NERFINISHED ⓘ Intel Stratix 10 FPGAs NERFINISHED ⓘ Platform Designer (Qsys successor) NERFINISHED ⓘ Signal Tap logic analyzer NERFINISHED ⓘ SystemVerilog NERFINISHED ⓘ VHDL NERFINISHED ⓘ Verilog HDL NERFINISHED ⓘ advanced optimization algorithms ⓘ advanced timing analysis ⓘ design partitioning ⓘ design space exploration ⓘ hierarchical design flows ⓘ high-performance place-and-route ⓘ incremental compilation ⓘ partial reconfiguration ⓘ power analysis ⓘ static timing analysis ⓘ |
| targetUser |
ASIC prototyping teams
ⓘ
FPGA design engineers ⓘ high-performance computing designers ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.