Rome
E658518
Rome is the codename for a generation of AMD EPYC server processors based on the Zen 2 microarchitecture, known for significant improvements in performance and efficiency over its predecessors.
Statements (46)
| Predicate | Object |
|---|---|
| instanceOf |
AMD EPYC microarchitecture codename
ⓘ
server processor family ⓘ |
| announced | August 2019 ⓘ |
| architectureFamily | x86-64 NERFINISHED ⓘ |
| basedOnMicroarchitecture | Zen 2 NERFINISHED ⓘ |
| chipletDesign | true ⓘ |
| codenameFor | second-generation AMD EPYC processors ⓘ |
| coreDieProcessNode | 7 nm ⓘ |
| ioDieProcessNode | 12 nm ⓘ |
| launchYear | 2019 ⓘ |
| manufacturer |
AMD
NERFINISHED
ⓘ
Advanced Micro Devices NERFINISHED ⓘ |
| marketSegment |
data center
ⓘ
server ⓘ |
| maxCoreCountPerCPU | 64 ⓘ |
| maxMemoryChannelsPerSocket | 8 ⓘ |
| maxPCIeLanesPerSocket | 128 ⓘ |
| maxThreadCountPerCPU | 128 ⓘ |
| memoryType | DDR4 ⓘ |
| notableImprovementOverPredecessor |
higher core counts
ⓘ
higher memory bandwidth ⓘ improved performance per watt ⓘ more PCIe lanes ⓘ |
| predecessor | Naples NERFINISHED ⓘ |
| processNode | 7 nm ⓘ |
| processNodeSupplier | TSMC NERFINISHED ⓘ |
| socket | Socket SP3 NERFINISHED ⓘ |
| successor | Milan NERFINISHED ⓘ |
| supportsECCMemory | true ⓘ |
| supportsInstructionSet |
AES-NI
ⓘ
AVX2 NERFINISHED ⓘ FMA3 ⓘ SHA ⓘ SSE4.2 ⓘ x86-64 ⓘ |
| supportsMultiSocketConfiguration | up to 2 sockets ⓘ |
| supportsPCIeVersion | PCIe 4.0 ⓘ |
| supportsSecurityFeature |
SEV-ES
NERFINISHED
ⓘ
SME NERFINISHED ⓘ Secure Encrypted Virtualization NERFINISHED ⓘ |
| supportsVirtualization |
AMD-V
NERFINISHED
ⓘ
AMD-Vi NERFINISHED ⓘ |
| targetUseCases |
cloud computing
ⓘ
enterprise servers ⓘ high-performance computing ⓘ virtualization ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.