Tessent
E656353
Tessent is a suite of design-for-test and yield analysis tools from Mentor Graphics (now Siemens EDA) used to improve the testability and reliability of integrated circuits.
Statements (48)
| Predicate | Object |
|---|---|
| instanceOf |
design-for-test tool
ⓘ
electronic design automation tool suite ⓘ yield analysis tool ⓘ |
| applicationDomain |
integrated circuit design
ⓘ
semiconductor test ⓘ yield analysis ⓘ |
| developer |
Mentor Graphics
NERFINISHED
ⓘ
Siemens EDA NERFINISHED ⓘ |
| feature |
automatic test pattern generation
ⓘ
built-in self-test insertion ⓘ diagnosis-driven yield analysis ⓘ in-system test support ⓘ layout-aware diagnosis ⓘ safety mechanism verification ⓘ scan compression ⓘ |
| formerlyOwnedBy | Mentor Graphics NERFINISHED ⓘ |
| hasComponent |
Tessent BoundaryScan
NERFINISHED
ⓘ
Tessent DefectSim NERFINISHED ⓘ Tessent Diagnosis NERFINISHED ⓘ Tessent IJTAG NERFINISHED ⓘ Tessent LogicBIST NERFINISHED ⓘ Tessent MemoryBIST NERFINISHED ⓘ Tessent Safety NERFINISHED ⓘ Tessent Scan NERFINISHED ⓘ Tessent YieldInsight NERFINISHED ⓘ |
| industry | electronic design automation ⓘ |
| market |
automotive ICs
ⓘ
consumer electronics ICs ⓘ data center ICs ⓘ networking ICs ⓘ |
| ownedBy | Siemens NERFINISHED ⓘ |
| partOf | Siemens EDA portfolio NERFINISHED ⓘ |
| purpose |
improve reliability of integrated circuits
ⓘ
improve testability of integrated circuits ⓘ optimize manufacturing yield ⓘ |
| supportsProcess |
design-for-test
ⓘ
failure analysis ⓘ production test ⓘ yield learning ⓘ |
| supportsStandard |
IEEE 1149.1
NERFINISHED
ⓘ
IEEE 1500 NERFINISHED ⓘ IEEE 1687 NERFINISHED ⓘ |
| targetHardware |
advanced process node ICs
ⓘ
application-specific integrated circuit ⓘ system-on-chip ⓘ |
| usedBy |
integrated circuit designers
ⓘ
semiconductor companies ⓘ test engineers ⓘ |
Referenced by (1)
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