ModelSim

E656349

ModelSim is a widely used hardware description language (HDL) simulation and debugging environment for VHDL, Verilog, and SystemVerilog designs.

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Statements (57)

Predicate Object
instanceOf HDL simulator
electronic design automation tool
software product
developedBy Mentor Graphics NERFINISHED
hasEdition ModelSim DE NERFINISHED
ModelSim PE NERFINISHED
ModelSim PE Student Edition NERFINISHED
ModelSim SE NERFINISHED
hasFeature Tcl scripting interface
assertion-based verification support
breakpoints
code coverage analysis
command-line interface
do-file automation
foreign language interface
graphical user interface
graphical waveform viewer
incremental compilation
macro recording
mixed-language simulation
multi-library management
optimized simulation kernel
project management environment
signal forcing
source-level debugging
testbench debugging
watch windows
waveform logging
hasStudentVersion true
integratesWith Intel Quartus Prime NERFINISHED
Xilinx Vivado NERFINISHED
other EDA tools via standard interfaces
licenseType commercial
ownedBy Siemens EDA NERFINISHED
partOf Siemens EDA tool portfolio NERFINISHED
previousOwner Mentor Graphics NERFINISHED
runsOn Linux NERFINISHED
Windows NERFINISHED
supports UVM-based verification (via SystemVerilog)
testbench automation
transaction-level modeling
supportsLanguage SystemVerilog NERFINISHED
VHDL NERFINISHED
Verilog NERFINISHED
supportsStandard IEEE 1076 VHDL NERFINISHED
IEEE 1364 Verilog NERFINISHED
IEEE 1800 SystemVerilog NERFINISHED
usedFor ASIC design verification
FPGA design verification
debugging SystemVerilog designs
debugging VHDL designs
debugging Verilog designs
functional simulation of digital designs
verification of HDL designs
usedIn FPGA development flows
academic research and teaching
semiconductor industry

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