Calibre
E656348
Calibre is an electronic design automation tool suite from Mentor Graphics widely used for physical verification and design rule checking in semiconductor chip design.
Statements (50)
| Predicate | Object |
|---|---|
| instanceOf |
electronic design automation tool
ⓘ
software suite ⓘ |
| component |
Calibre CMPAnalyzer
NERFINISHED
ⓘ
Calibre DESIGNrev NERFINISHED ⓘ Calibre DRC NERFINISHED ⓘ Calibre LFD NERFINISHED ⓘ Calibre LVS NERFINISHED ⓘ Calibre PERC NERFINISHED ⓘ Calibre YieldEnhancer NERFINISHED ⓘ Calibre nmDRC NERFINISHED ⓘ Calibre nmLFD NERFINISHED ⓘ Calibre nmLVS ⓘ Calibre xACT NERFINISHED ⓘ Calibre xRC NERFINISHED ⓘ |
| developer |
Mentor Graphics
NERFINISHED
ⓘ
Siemens EDA NERFINISHED ⓘ |
| domain | electronic design automation ⓘ |
| fileFormatSupport |
DEF
ⓘ
GDSII ⓘ LEF NERFINISHED ⓘ OASIS NERFINISHED ⓘ |
| integratesWith |
Cadence Virtuoso
NERFINISHED
ⓘ
Mentor Graphics Olympus-SoC NERFINISHED ⓘ Synopsys IC Compiler NERFINISHED ⓘ place-and-route tools ⓘ |
| notableFeature |
foundry-qualified rule decks
ⓘ
scalable performance for large designs ⓘ signoff-quality physical verification ⓘ |
| ownedBy | Siemens NERFINISHED ⓘ |
| supportsNode |
FinFET technologies
ⓘ
advanced process nodes ⓘ planar CMOS technologies ⓘ |
| supportsTask |
chemical mechanical polishing analysis
ⓘ
design rule checking ⓘ layout versus schematic ⓘ lithography process checking ⓘ parasitic extraction ⓘ |
| targetUser |
IC layout engineer
ⓘ
physical design engineer ⓘ verification engineer ⓘ |
| usedBy |
IDMs
ⓘ
fabless semiconductor companies ⓘ foundries ⓘ |
| usedFor |
design rule checking
ⓘ
layout versus schematic checking ⓘ lithography checking ⓘ parasitic extraction ⓘ physical verification ⓘ |
| usedIn |
integrated circuit design
ⓘ
semiconductor manufacturing ⓘ |
Referenced by (1)
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