Washington Treaty
E254247
The Washington Treaty is an international agreement that establishes intellectual property protection standards for the layout designs of integrated circuits.
All labels observed (1)
| Label | Occurrences |
|---|---|
| Washington Treaty canonical | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T2309119 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
Target entity: Washington Treaty Context triple: [Washington Treaty on Intellectual Property in Respect of Integrated Circuits, shortName, Washington Treaty]
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A.
Four-Power Treaty
The Four-Power Treaty was a 1921 agreement between the United States, Britain, Japan, and France to consult one another in the event of disputes in the Pacific, helping to stabilize power relations and replace the Anglo-Japanese Alliance.
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B.
Kellogg–Briand Pact
The Kellogg–Briand Pact was a 1928 international agreement in which numerous nations renounced war as an instrument of national policy, symbolizing idealistic efforts to secure peace in the interwar period.
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C.
Élysée Treaty
The Élysée Treaty is a landmark 1963 agreement that cemented postwar reconciliation and close political cooperation between France and West Germany.
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D.
Five-Power Treaty
The Five-Power Treaty was a 1922 naval disarmament agreement among major world powers that limited battleship construction and aimed to prevent an arms race at sea.
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E.
Tripartite Pact
The Tripartite Pact was a World War II alliance agreement that formally united Germany, Italy, and Japan into the Axis powers against the Allied nations.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Target entity: Washington Treaty Target entity description: The Washington Treaty is an international agreement that establishes intellectual property protection standards for the layout designs of integrated circuits.
-
A.
Four-Power Treaty
The Four-Power Treaty was a 1921 agreement between the United States, Britain, Japan, and France to consult one another in the event of disputes in the Pacific, helping to stabilize power relations and replace the Anglo-Japanese Alliance.
-
B.
Kellogg–Briand Pact
The Kellogg–Briand Pact was a 1928 international agreement in which numerous nations renounced war as an instrument of national policy, symbolizing idealistic efforts to secure peace in the interwar period.
-
C.
Élysée Treaty
The Élysée Treaty is a landmark 1963 agreement that cemented postwar reconciliation and close political cooperation between France and West Germany.
-
D.
Five-Power Treaty
The Five-Power Treaty was a 1922 naval disarmament agreement among major world powers that limited battleship construction and aimed to prevent an arms race at sea.
-
E.
Tripartite Pact
The Tripartite Pact was a World War II alliance agreement that formally united Germany, Italy, and Japan into the Axis powers against the Allied nations.
- F. None of above. chosen
Statements (47)
| Predicate | Object |
|---|---|
| instanceOf |
intellectual property treaty
ⓘ
international treaty ⓘ treaty on layout-designs of integrated circuits ⓘ |
| aimsTo |
harmonize protection of layout-designs of integrated circuits among states
ⓘ
prevent unauthorized copying of layout-designs of integrated circuits ⓘ promote innovation in semiconductor technology ⓘ |
| appliesTo |
integrated circuits
ⓘ
layout-designs embodied in integrated circuits ⓘ |
| defines |
layout-design of an integrated circuit
ⓘ
original layout-design ⓘ |
| excludesFromProtection |
concepts or methods underlying a layout-design
ⓘ
ideas, processes, systems, or techniques embodied in a layout-design ⓘ |
| field |
industrial property
ⓘ
intellectual property law ⓘ |
| hasAlternativeName |
treaty on intellectual property
ⓘ
surface form:
IPIC Treaty
Washington Treaty on Intellectual Property in Respect of Integrated Circuits ⓘ
surface form:
Treaty on Intellectual Property in Respect of Integrated Circuits
|
| hasLanguage |
Arabic
ⓘ
Chinese ⓘ English ⓘ French ⓘ Russian ⓘ Spanish ⓘ |
| hasProtectionCriterion |
fixation of layout-design in a material form
ⓘ
originality of layout-design ⓘ |
| hasProtectionTerm | limited duration of exclusive rights in layout-designs ⓘ |
| hasShortName | Washington Treaty on Intellectual Property in Respect of Integrated Circuits ⓘ |
| influenced | national laws on layout-designs of integrated circuits ⓘ |
| isPartOf | international framework for protection of intellectual property in technology ⓘ |
| isRelatedTo |
World Intellectual Property Organization
ⓘ
protection of semiconductor chip topographies ⓘ |
| legalDomain | international intellectual property law ⓘ |
| protects | right holders of layout-designs of integrated circuits ⓘ |
| providesFor |
limitations for acts done privately and for non-commercial purposes
ⓘ
limitations for analysis, evaluation, or teaching of layout-designs ⓘ limitations for creation of an original layout-design based on analysis of another layout-design ⓘ minimum scope of exclusive rights in layout-designs ⓘ national treatment for foreign right holders ⓘ possible compulsory licenses or government use under certain conditions ⓘ |
| regulates |
conditions for protection of layout-designs of integrated circuits
ⓘ
exclusive rights in layout-designs of integrated circuits ⓘ limitations and exceptions to protection of layout-designs of integrated circuits ⓘ minimum standards of protection for layout-designs of integrated circuits ⓘ protection of layout-designs of integrated circuits ⓘ term of protection for layout-designs of integrated circuits ⓘ |
| requires | member states to provide legal remedies against infringement of protected layout-designs ⓘ |
| subjectMatter |
layout-designs of integrated circuits
ⓘ
topographies of integrated circuits ⓘ |
How these facts were elicited
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Subject: Washington Treaty Description of subject: The Washington Treaty is an international agreement that establishes intellectual property protection standards for the layout designs of integrated circuits.
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.