HyperTransport 3.0
E1033649
HyperTransport 3.0 is a high-speed, low-latency point-to-point interconnect technology used to link processors and other system components in modern computer architectures.
All labels observed (3)
| Label | Occurrences |
|---|---|
| HyperTransport | 1 |
| HyperTransport 3.0 canonical | 1 |
| HyperTransport interconnect | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T13320212 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: HyperTransport 3.0 Context triple: [Phenom, supportsFeature, HyperTransport 3.0]
-
A.
VIA C3
VIA C3 is a family of low-power x86-compatible microprocessors from VIA Technologies, designed primarily for energy-efficient and embedded computing applications.
-
B.
PCI-X
PCI-X is an older high-speed parallel computer expansion bus standard used mainly in servers and workstations before being superseded by PCI Express.
-
C.
Intel 430FX chipset
The Intel 430FX chipset is an early Pentium-era core logic chipset from Intel that provided support for features like PCI, EDO/FPM DRAM, and basic system I/O on mid-1990s desktop motherboards.
-
D.
Apollo Lake platform
The Apollo Lake platform is Intel’s low-power system-on-chip family for entry-level PCs and embedded devices, built around the Goldmont CPU microarchitecture.
-
E.
3DNow!
3DNow! is a SIMD instruction set extension developed by AMD to accelerate floating-point and multimedia processing, particularly for 3D graphics and gaming workloads.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: HyperTransport 3.0 Target entity description: HyperTransport 3.0 is a high-speed, low-latency point-to-point interconnect technology used to link processors and other system components in modern computer architectures.
-
A.
VIA C3
VIA C3 is a family of low-power x86-compatible microprocessors from VIA Technologies, designed primarily for energy-efficient and embedded computing applications.
-
B.
PCI-X
PCI-X is an older high-speed parallel computer expansion bus standard used mainly in servers and workstations before being superseded by PCI Express.
-
C.
Intel 430FX chipset
The Intel 430FX chipset is an early Pentium-era core logic chipset from Intel that provided support for features like PCI, EDO/FPM DRAM, and basic system I/O on mid-1990s desktop motherboards.
-
D.
Apollo Lake platform
The Apollo Lake platform is Intel’s low-power system-on-chip family for entry-level PCs and embedded devices, built around the Goldmont CPU microarchitecture.
-
E.
3DNow!
3DNow! is a SIMD instruction set extension developed by AMD to accelerate floating-point and multimedia processing, particularly for 3D graphics and gaming workloads.
- F. None of above. chosen
Statements (49)
| Predicate | Object |
|---|---|
| instanceOf |
computer bus standard
ⓘ
point-to-point interconnect ⓘ system interconnect technology ⓘ |
| applicationDomain |
CPU-to-CPU interconnect
ⓘ
CPU-to-chipset interconnect ⓘ system-on-chip interconnect ⓘ |
| backwardCompatibleWith |
HyperTransport 1.x
ⓘ
HyperTransport 2.0 NERFINISHED ⓘ |
| connects |
I/O controllers
ⓘ
chipsets ⓘ processors ⓘ system components ⓘ |
| dataRatePerDirection | up to 5.2 GT/s ⓘ |
| designedFor |
high-speed processor interconnect
ⓘ
low-latency communication ⓘ |
| developedBy | HyperTransport Consortium NERFINISHED ⓘ |
| directionality | full-duplex ⓘ |
| follows | HyperTransport 2.0 NERFINISHED ⓘ |
| layerModel | packet-based protocol ⓘ |
| maxLinkWidth | 32 bits ⓘ |
| partOf | HyperTransport specification NERFINISHED ⓘ |
| precedes | HyperTransport 3.1 NERFINISHED ⓘ |
| signaling | double data rate ⓘ |
| standardType | open industry standard ⓘ |
| supports |
coherent links
ⓘ
error detection ⓘ hot-plug capability ⓘ link frequency scaling ⓘ link width scaling ⓘ link-level flow control ⓘ non-coherent links ⓘ power management features ⓘ |
| supportsLinkWidth |
16 bits
ⓘ
2 bits ⓘ 32 bits ⓘ 4 bits ⓘ 8 bits ⓘ |
| targetCharacteristic |
high bandwidth
ⓘ
low latency ⓘ low power consumption ⓘ |
| topology | point-to-point ⓘ |
| usedBy |
AMD processors
NERFINISHED
ⓘ
server-class motherboards ⓘ some NVIDIA chipsets ⓘ |
| usedIn |
computer architectures
ⓘ
high-performance computing systems ⓘ multiprocessor systems ⓘ server platforms ⓘ workstation platforms ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: HyperTransport 3.0 Description of subject: HyperTransport 3.0 is a high-speed, low-latency point-to-point interconnect technology used to link processors and other system components in modern computer architectures.
Referenced by (3)
Full triples — surface form annotated when it differs from this entity's canonical label.
this entity surface form:
HyperTransport interconnect
subject surface form:
AMD Athlon 64
this entity surface form:
HyperTransport