HyperTransport 3.0

E1033649

HyperTransport 3.0 is a high-speed, low-latency point-to-point interconnect technology used to link processors and other system components in modern computer architectures.

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Observed surface forms (2)

Surface form Occurrences
HyperTransport 1
HyperTransport interconnect 1

Statements (49)

Predicate Object
instanceOf computer bus standard
point-to-point interconnect
system interconnect technology
applicationDomain CPU-to-CPU interconnect
CPU-to-chipset interconnect
system-on-chip interconnect
backwardCompatibleWith HyperTransport 1.x
HyperTransport 2.0 NERFINISHED
connects I/O controllers
chipsets
processors
system components
dataRatePerDirection up to 5.2 GT/s
designedFor high-speed processor interconnect
low-latency communication
developedBy HyperTransport Consortium NERFINISHED
directionality full-duplex
follows HyperTransport 2.0 NERFINISHED
layerModel packet-based protocol
maxLinkWidth 32 bits
partOf HyperTransport specification NERFINISHED
precedes HyperTransport 3.1 NERFINISHED
signaling double data rate
standardType open industry standard
supports coherent links
error detection
hot-plug capability
link frequency scaling
link width scaling
link-level flow control
non-coherent links
power management features
supportsLinkWidth 16 bits
2 bits
32 bits
4 bits
8 bits
targetCharacteristic high bandwidth
low latency
low power consumption
topology point-to-point
usedBy AMD processors NERFINISHED
server-class motherboards
some NVIDIA chipsets
usedIn computer architectures
high-performance computing systems
multiprocessor systems
server platforms
workstation platforms

Referenced by (3)

Full triples — surface form annotated when it differs from this entity's canonical label.

Phenom supportsFeature HyperTransport 3.0
AMD Opteron feature HyperTransport 3.0
this entity surface form: HyperTransport interconnect
AMD Athlon 64 processors supportsFeature HyperTransport 3.0
subject surface form: AMD Athlon 64
this entity surface form: HyperTransport