HBM2
E1033643
HBM2 is a high-bandwidth second-generation stacked memory technology used in advanced GPUs and accelerators to provide very fast, energy-efficient data access.
Statements (47)
| Predicate | Object |
|---|---|
| instanceOf |
JEDEC memory standard
ⓘ
high-bandwidth memory standard ⓘ stacked DRAM technology ⓘ |
| applicationDomain |
graphics rendering
ⓘ
high‑performance data analytics ⓘ machine learning ⓘ scientific computing ⓘ |
| comparedTo | GDDR5 NERFINISHED ⓘ |
| dataRatePerPin | up to 2 Gbit/s per pin ⓘ |
| follows | HBM NERFINISHED ⓘ |
| generation | second generation HBM ⓘ |
| hasProperty |
3D stacked
ⓘ
energy efficient ⓘ high bandwidth ⓘ low power consumption ⓘ short interconnect distance to processor ⓘ wide I/O interface ⓘ |
| interconnectTechnology |
TSVs
ⓘ
through‑silicon vias ⓘ |
| introducedAround | 2016 ⓘ |
| maxBandwidthPerStack | up to 256 GB/s ⓘ |
| maxCapacityPerStack | up to 8 GB ⓘ |
| memoryType | DRAM ⓘ |
| offers |
higher bandwidth than GDDR5
ⓘ
lower power per bit than GDDR5 ⓘ |
| optimizedFor |
high memory bandwidth workloads
ⓘ
parallel processing ⓘ |
| packaging |
2.5D integration
ⓘ
silicon interposer ⓘ |
| provides |
high memory bandwidth close to compute die
ⓘ
very fast data access ⓘ |
| stackHeight | up to 8 DRAM dies ⓘ |
| standardizedBy | JEDEC NERFINISHED ⓘ |
| successor |
HBM2E
NERFINISHED
ⓘ
HBM3 NERFINISHED ⓘ |
| typicalBusWidthPerStack | 1024‑bit GENERATED ⓘ |
| usedBy |
AI accelerator cards
ⓘ
AMD GPUs NERFINISHED ⓘ NVIDIA GPUs NERFINISHED ⓘ |
| usedIn |
AI accelerators
ⓘ
GPUs ⓘ accelerators ⓘ data center accelerators ⓘ graphics processing units ⓘ high‑performance computing systems ⓘ networking equipment ⓘ supercomputers ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.