AMD Instinct MI100
E1033641
AMD Instinct MI100 is a high-performance data center GPU accelerator from AMD designed primarily for high-performance computing (HPC) and AI workloads.
Observed surface forms (1)
| Surface form | Occurrences |
|---|---|
| AMD Instinct | 1 |
Statements (50)
| Predicate | Object |
|---|---|
| instanceOf |
AMD Instinct accelerator
ⓘ
GPU accelerator ⓘ data center GPU ⓘ |
| architecture | CDNA NERFINISHED ⓘ |
| brand | AMD Instinct NERFINISHED ⓘ |
| category | GPGPU ⓘ |
| codename | Arcturus NERFINISHED ⓘ |
| cooling | active air cooling ⓘ |
| designedFor | data centers ⓘ |
| formFactor | dual-slot PCIe card ⓘ |
| foundry | TSMC NERFINISHED ⓘ |
| interface | PCIe 4.0 x16 ⓘ |
| launchDate | November 2020 ⓘ |
| manufacturer | AMD NERFINISHED ⓘ |
| marketSegment | data center ⓘ |
| memoryBandwidth | 1228 GB/s ⓘ |
| memoryBusWidth | 4096-bit ⓘ |
| memoryCapacity | 32 GB ⓘ |
| memoryType | HBM2 ⓘ |
| peakBF16Performance | 46.1 TFLOPS ⓘ |
| peakFP16Performance | 46.1 TFLOPS ⓘ |
| peakFP32Performance | 23.1 TFLOPS ⓘ |
| peakFP64Performance | 11.5 TFLOPS ⓘ |
| predecessor | AMD Radeon Instinct MI60 NERFINISHED ⓘ |
| processNode | 7 nm ⓘ |
| successor | AMD Instinct MI200 series NERFINISHED ⓘ |
| supports |
BF16 operations
ⓘ
ECC memory ⓘ FP16 vector operations ⓘ FP32 vector operations ⓘ FP64 vector operations ⓘ HIP ⓘ Linux NERFINISHED ⓘ Matrix Cores ⓘ OpenCL NERFINISHED ⓘ PCI Express 4.0 ⓘ PCIe peer-to-peer ⓘ ROCm NERFINISHED ⓘ SR-IOV NERFINISHED ⓘ mixed-precision compute ⓘ multi-GPU configurations ⓘ |
| targetWorkloads |
artificial intelligence
ⓘ
high-performance computing ⓘ machine learning ⓘ scientific computing ⓘ |
| TDP | 300 W ⓘ |
| useCase |
AI inference
ⓘ
AI training ⓘ HPC clusters ⓘ data analytics ⓘ |
Referenced by (2)
Full triples — surface form annotated when it differs from this entity's canonical label.
this entity surface form:
AMD Instinct
subject surface form:
AMD Instinct